Photolithography is a fabrication technique that is employed for use in a number of industries, including the semiconductor processing industry. Specifically, photolithography uses an energy source such as ultraviolet (UV) light, x-ray wavelength, other wavelengths of radiation, etc. to expose selected regions of a surface. In one common technique, the surface includes a semiconductor wafer such as silicon that has been coated with a resist material. The resist material properties are locally changed when exposed to the energy source, which allows selected regions of the resist material to remain, while unwanted regions of the resist material are removed.
In one method of photolithography, a pattern of features is created on a reticle or mask, and the pattern on the reticle is focused onto a semiconductor surface using optics that adjust the scale of the pattern on the reticle to fit the semiconductor surface. In the semiconductor industry, there is an ever present pressure to reduce the size of features in the pattern to increase the density of patterned features packed into the same semiconductor surface area. In one example industry, manufacturers of random access memory chips such as dynamic random access memory (DRAM) strive to put more storage cells onto a single chip.
As feature size decreases, photolithography of smaller and smaller features becomes more and more difficult. One of the key parameters in lithography is the focal parameter. During processing of a wafer several factors may cause variations in the focal parameter of the lithographic system. These factors may include lens heating, non-planarity of the wafer, wafer tilt or lens aberrations, among others. At sub-wavelength geometries, it is necessary to verify that each mask design prints as expected before it goes through mask manufacturing and wafer production. To assure the wafer manufacturer that the mask as designed will produce flawless wafers, silicon designers have developed simulation software to predict the results of the wafer fabrication. For example, Synopsys' SiVL (Silicon vs. Layout Verification Tool) software is an industry leader in design for manufacturability (DFM) software. Other software tools include simulation engines for Optical Proximity Correction (OPC) and Resolution Enhancement Techniques (RET).
Current simulation software may operate with individually generated defocus models and generate reports at each discrete defocus parameter. The time required to run a single simulation for a single defocus parameter is measured in hours and may take a full day depending on the layout size and complexity of the chip. Therefore, the number of defocus parameters that may be calculated is often limited due to time and resource restraints. Many times the calculations are limited to the outermost thresholds of defocus and a nominal defocus value, sometimes called best-focus value. This prevents the ability to run full-focus window simulations. In addition, defocus values other than the nominal one (i.e., the best-focus value) may result in the greatest errors and these errors may not be discovered until the wafer has already been run. As a result, a loss of significant resources and time may occur from the current simulation practices.